Integrated circuit memory devices typically include one or more arrays of memory cells that store data. The data is either read from or written to the memory cell using data communication connections. Some typical memory devices include random access memories (RAM), dynamic random access memories (DRAM), Synchronous DRAM (SDRAM), static RAM (SRAM), and non-volatile memories such as FLASH.
A memory data array is often internally organized as a page of data containing n words with each word containing a number of bits equal to the number of data communication connections (DQ's). During production of the memory devices, the individual memory cells need to be tested. One of the tests may be a write verification test.
The write verification test involves writing a known pattern of data (e.g., a pattern of ones and zeroes) to the memory array. The data can be read one word at a time and compared bit-by-bit to the pattern of data originally input to the memory array. If each bit in a particular position of each word of the output data matches the corresponding bit of the input pattern, the devices passes the test. A mismatch between any bit of any word of the output data and the input pattern indicates a failure.
A problem with such a test is that as the density of the memory arrays increase, the time needed to fully test the memory array also increases. Since the memory manufacturer has to test a large number of memory devices, even a small increase in test time multiplied by the large number of memory devices, creates a problem for the manufacturer.
One technique that can be used to decrease test time is data compression. Data read from multiple memory cells are compressed into a smaller number of data bits. Thus, less time is required for a given number of memory cells when implementing data compression. Data compression read circuitry is usually designed in such a way that does not affect the performance of write or read non-test operations. The data compression read path only operates in test mode and is in parallel to the non-test read path.
Typical data compression techniques are based on a ratioed logic approach to data compression. The ratioed logic approach is well know in the art and is not discussed further. Ratioed logic is typically limited to perform compression in a range of ten words. This limits the amount of compression that can be accomplished in order to reduce the testing time.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an alternative data compression read scheme.